`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:42:54 07/02/2015
// Design Name:   Etapa4
// Module Name:   D:/Libraries/Documents/Ingenieria en computacion/Arquitectura Computadoras/TrabajoFinalArquitectura/trunk/Final-Mips/Etapa4Test.v
// Project Name:  Final-Mips
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Etapa4
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Etapa4Test;

	// Inputs
	reg [31:0] salidaALU;
	reg zeroFlag;
	reg [31:0] salidaAdder;
	reg [4:0] salidaMux;
	reg [31:0] Data2;
	reg RegWrite;
	reg PCSrc1;
	reg MemRead1;
	reg [3:0] MemWrite1;
	reg MemToReg1;
	reg [2:0] LoadOp1;
	reg jmp1;
	reg clk;

	// Outputs
	wire [31:0] salidaE4;
	wire PCSrc;
	wire [31:0] salidaAdder1;
	wire [4:0] salidaMux1;
	wire RegWrite1;
	wire MemToReg;
	wire jmp;
	wire [31:0] ALUdata;

	// Instantiate the Unit Under Test (UUT)
	Etapa4 uut (
		.salidaALU(salidaALU), 
		.zeroFlag(zeroFlag), 
		.salidaAdder(salidaAdder), 
		.salidaMux(salidaMux), 
		.Data2(Data2), 
		.RegWrite(RegWrite), 
		.PCSrc1(PCSrc1), 
		.MemRead1(MemRead1), 
		.MemWrite1(MemWrite1), 
		.MemToReg1(MemToReg1), 
		.LoadOp1(LoadOp1), 
		.jmp1(jmp1), 
		.clk(clk), 
		.salidaE4(salidaE4), 
		.PCSrc(PCSrc), 
		.salidaAdder1(salidaAdder1), 
		.salidaMux1(salidaMux1), 
		.RegWrite1(RegWrite1), 
		.MemToReg(MemToReg), 
		.jmp(jmp),
		.ALUdata(ALUdata)
	);

	initial begin
		// Initialize Inputs
		salidaALU = 0;
		zeroFlag = 0;
		salidaAdder = 0;
		salidaMux = 0;
		Data2 = 0;
		RegWrite = 0;
		PCSrc1 = 0;
		MemRead1 = 0;
		MemWrite1 = 0;
		MemToReg1 = 0;
		LoadOp1 = 0;
		jmp1 = 0;
		clk = 0;

		// Wait 100 ns for global reset to finish
		#100;
		// Add stimulus here
		salidaALU = 32'h ffffffff;
		zeroFlag = 0;
		salidaAdder = 32'h 00004080;
		salidaMux = 5'h 02;
		Data2 = 32'h 0000ffff;
		RegWrite = 1;
		PCSrc1 = 0;
		MemRead1 = 1;
		MemWrite1 = 4'b 1111;
		MemToReg1 = 0;
		LoadOp1 = 3'b 011;
		jmp1 = 0;
		
		//Agregamos Datos a la memoria
		
		
		
	
	end
 
 always begin
 #1; clk = ~clk;
 end
 
endmodule

